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Altera_Forum
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8 years ago

interfacing to epcq256 through fpga

Hello, I've posted this before but I'm trying to interfacing to the epcq256 via the fpga in order to store a counter on the epcq. I'm using the ASMI parallel core in order to transfer data to a...
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Altera_Forum
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8 years ago

Hi AMalexander,

Check the busy signal before sending a new command. When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself(IP) before executing the next command

For more information click here (https://www.altera.co.jp/ja_jp/pdfs/literature/ug/ug_altasmi_parallel.pdf)

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)