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Hi,
If you're chip uses LVDS signalling, you can interface it to FPGA via the HSMC bridge. Make sure the input pins for these signals are set as LVDS in the pin planner. This way you will be able to read in the LVDS data from the chip into the FPGA. The LVDS IO at the FPGA will convert the differential signals to single-ended ones internally at the IOBUF level. Thus you will get single-ended signals from the LVDS IO inside the FPGA and you can use it for other logical purposes in the core logic.
Does this answer your question?
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Hi,
So it means we have to connect the LVDS I/O pins of FPGA to the HSMC Connector which automatically convert the differential signals to single-ended ones?
And do you have the required VHDL Interfacing code for FPGA with AFE. It will help for any reference.
Best Regards,
Nimish
Honored Contributor
