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mamuneeb332's avatar
mamuneeb332
Icon for New Contributor rankNew Contributor
2 years ago

Interfacing External Memory (DDR4) with Arria 10 through EMIF IP

Hello !
With the help of External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide, i am able to see the PNF(pass-not-Fail) bits in the Signal Tap Logic Analyzer. Additionally, I have obtained some data from the Efficiency Monitor using the EMIF Debug Toolkit (as shown in the attached snapshot). However, I am currently unable to determine the speed of data transfer between the FPGA and DDR4 memory, specifically the speed of reads or writes. I am seeking assistance in this matter.

Please help me with this.

Thank You.

2 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello sir,


    You can calculate the bandwidth as follow:

    Bandwidth = data width (bits) x data transfer rate (1/s) x system efficiency

    For example, the DDR interface has 16 bits of data width running at 200MHz frequency with 70% efficiency.

    Bandwidth = 16 bits x 2 clock edge(double data rate) x 200MHz x 70% = 4.48 Gbps.


    Regards,

    Adzim


  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.