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Altera_Forum's avatar
Altera_Forum
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15 years ago

interface with niosII processor

Hi,

Is it possible the interface of ram IP core (from megawizard plug in manager) with niosII processor and VHDL as target HDL.

I have generated NiosII processor with 4K of on chip ram.For this generated processor I want to connect RAM IP core. How to instantiate the niosII generated file into quartusII project. How to port map the instantiate file..

Pls help me.......

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    hi,

    can you pls tell me how to do it. It will help me lot.

    thank you
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    It's a lot easier to add your ram IP core as a component inside SOPC builder rather than using a component from the megawizard. If you really want to use a megawivard component, you'll have to write some wrapper HDL code to integrate it in SOPC builder.