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Altera_Forum's avatar
Altera_Forum
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11 years ago

interface with DDR external memory using IP-core

Hi all!

I'm working with Cyclone V, my aim is to use DDR memory. Am I right that I need to create my own controller and use ALTDQ_DQS2 IP Core as PHY?

I mean that Altera removed support of DDR memory controller in Cyclone V.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Correct, Altera DDR controller is not supported on Cyclone V.

    If this is a new design, my suggestion would be to use Cyclone V with Hard Memory Controller and select a compatible memory device.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Thanks for your answer, ted.

    No, design hasn't the ability to use HMC. I think that I have to use ALTDQ_DQS2 and custom VHDL_or_Verilog Controller