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Altera_Forum
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14 years ago

Interface of FPGA to Microcontroler IRQ, pooling or delay

Hi, all General question especial to experienced developers regarding CPU - FPGA interface. I Would be very glad to receive any comments or thoughts share. Say, there is some measurem...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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since your cpu task is forced 1ms busy in the polling loop.

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Actually I would not expect the CPU to be stuck in a polling loop for 1 ms churning away doing nothing. Rather I would expect the CPU to come back periodically as part of a larger polling cycle (i.e. maybe the processor wakes up once every XX ms to see if there is anything that needs attention).

Kevin Jennings