Interface of FPGA to Microcontroler IRQ, pooling or delay

Just my 2 cents:

I agree with Kevin in the fact solution# 2 (polling) is the normal approach.

But I think this is the simplest solution, not necessarily the best one.

It's the simplest because it requires no additional hw and you easily implement the poll function in sw.

Anyway, as Kevin remarked, this is not the best if your system is time critical, besides being rather inefficient, since your cpu task is forced 1ms busy in the polling loop.

This gets worse if your measurement has to be performed often.

So, if you have strong requirements on cpu time for other tasks and you need frequent measurements, the irq solution should be privileged, at the expense of a bit more complex hardware.

I'd exclude the fixed time solution# 1, since it has inherently the same defects of the polling as well as being hw dependent: whenever you change your fpga function you possibly must tune the delay time for optimal performance.

In the case you choose the polling method, I'd suggest you implement the completion status signal as a microprocessor pio/flag-input rather than a status bit on a MM register: this will be faster and more energy efficient because your cpu doesn't need to access the bus on every poll.

Regards

Cris