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Hi, all
General question especial to experienced developers regarding CPU - FPGA interface.
I Would be very glad to receive any comments or thoughts share.
Say, there is some measurement that the FPGA has to perform, This measurement takes no more then 1ms which is 1% of Microprocessor usual task duration.
The measurement starts by Microprocessor writing to some write only register implemented in FPGA.
After FPGA completes the measurement, the result is written to read only register in FPGA.
The question rises, how does Microprocessor know that the measurement is over, and result is valid?
There are three main possibilities
1. No indication from FPGA is provided, but the spec defines minimum delay that Microprocessor has to wait after triggering the measurement and before fetching results.
2. Pooling: Some sort of indication - say, another register, that has to be read to check for measurement completion.
3. Interrupt request.
How are usually things implemented, is there any legitimacy to choose the first possibility (seems as if it introduces unnecessary coupling...), or maybe pooling is usually preferred to Interrupt request? What would you choose?
Any Comments are welcome.
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- Presuming that this reading from the FPGA is not time sensitive thing then an interrupt would probably not be appropriate, regardless of the duration of time for the FPGA to complete the task.
- If there are other reasons why the processor would need to query the status of something else in the FPGA for things that are again not time sensitive, then polling of these registers would be the best approach.
- Setting a status bit to indicate completion of the task is the better approach. Otherwise the processor is required to keep track of the elapsed time...yes it certainly can do it, but ask yourself why should it? Then ask yourself how hard is it to set a status bit at the completion of the task that you are controlling anyway.
So# 2 is the best approach unless you have some time sensitive requirement that you haven't mentioned that might push you to# 3.
Kevin Jennings
Honored Contributor
