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There are three main possibilities
1. No indication from FPGA is provided, but the spec defines minimum delay that Microprocessor has to wait after triggering the measurement and before fetching results.
2. Pooling: Some sort of indication - say, another register, that has to be read to check for measurement completion.
3. Interrupt request.
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Implement the following;
1) An Avalon-MM slave set of registers with the following registers;
control register:
* enable
* mode = one-off, repeated
* interrupt enable
status register;
* done (for one-off mode)
repeated measurement period:
* a counter load value, eg. for 1ms repeat time
conversion register:
* a read-only register with the conversion result
2) Polled Mode:
You can implement polling by enabling one-shot mode, and reading the status register for the done bit. You then disable and re-enable the controller, and repeat.
3) IRQ Mode:
You can enable the interrupt, and when 'done' asserts, also have that status bit assert an IRQ on your processor. The processor IRQ can then disable/reenable the controller.
4) If you want more accurate time between measurements, then enable the controller in repeat mode, and set the logic up to give you an IRQ every conversion. The IRQ would just read the conversion, and leave it running.
If you were worried about losing conversion results, or you wanted to process blocks of conversions, then you can add a FIFO and have the hardware write results into the FIFO. Eg. think of how a serial port receiver operates.
Cheers,
Dave
Honored Contributor
