Interface LVDS signals to the FPGA cyclone V GX.

Hi Mateo,

Please find my response below:

1.Reading an old post here I realized that I obviously must assign the correct pin to each entry coming from the AFE5809evm to the FPGA through the HSMC-ADC-BRIDGE, I have them all assigned in paper, and using DIFFIO_RX_ I assign them one by one in the Quartus (Web edition 15.0), is that right ?.

Yes, correct.

2.On the other hand in the same post it mentions that the FPGA will convert the differential signal to single-ended internally at the IOBUFF level. What I do not understand is how to use the command mentioned above.

In the Quartus I create a new project, I am very sorry but it is my second project in this, I go to the assignment's window -> pins planner -> differential Pins -> DIFF Input with serdes, there I have all the pins available to be assigned, What I found is that the pin corresponding to FCLKM(LVDS frame clock x1 negative output) and FCLKP(LVDS frame clock x1 positive output) of the AFE5809evm will be connected to theHSMC_RXp16 / n16 pins respectively, would this be a problem in the future for the correct reading of the data?

You will need to configure the pin in pin planner to differential I/O Standard (LVDS and etc) depending on the pin. In order to do the "differential signal to single-ended", it might need to use our LVDS serdes IP. Please refer to link below for more information about the IP.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altlvds.pdf

Hope it helps.

Regards,

YL