Interface LVDS signals to the FPGA cyclone V GX.

Thank you so much SOoYL for answer me,

Reading an old post here I realized that I obviously must assign the correct pin to each entry coming from the AFE5809evm to the FPGA through the HSMC-ADC-BRIDGE, I have them all assigned in paper, and using DIFFIO_RX_ I assign them one by one in the Quartus (Web edition 15.0), is that right ?.

On the other hand in the same post it mentions that the FPGA will convert the differential signal to single-ended internally at the IOBUFF level. What I do not understand is how to use the command mentioned above.

In the Quartus I create a new project, I am very sorry but it is my second project in this, I go to the assignment's window -> pins planner -> differential Pins -> DIFF Input with serdes, there I have all the pins available to be assigned, What I found is that the pin corresponding to FCLKM(LVDS frame clock x1 negative output) and FCLKP(LVDS frame clock x1 positive output) of the AFE5809evm will be connected to the HSMC_RXp16 / n16 pins respectively, would this be a problem in the future for the correct reading of the data?

Those are all the signals I need por process :

• D1M to D8M ADC CH1 to CH8 LVDS negative output
• D1P to D8P ADC CH1 to CH8 LVDS positive output
• DCLKM LVDS bit clock (7x) negative output
• DCLKP LVDS bit clock (7x) positive output

In the figure we observe the corresponding pins to be received called DKp/m where K is the number of signals (8) and p/n positive and negative respectively.

Again I ask for mercy, since I find it very difficult to program in this language using the QUARTUS.

Regards,

Mateo