interface a module with avalon bus

Hi Roberto!

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Hi Philipp, sorry for but I disagree that, our poster is just a beginner and wrong coding can confuse a lot, yes your code has type conversion and can work, I seen no declaration just during check for operand type, addition on code from poster cannot be done using std_logic_vector.

VHDL is strong typed and far from be a simple language we are using here the HDL part so during learning need have hint and example to grasp how to implement right way without inferencing latch and or other trap of.

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What's your point? Making the Avalon signals anything else than std_logic_vector would be just as wrong, as the data on the bus can be anything, signed, unsigned, a bit pattern or even a floating-point value. The addition has explicit type conversions to unsigned, so it is clear how the operation is performed. And I have no idea where you suspect the inference of a latch. I just compiled the code and it is all fine, except for the already-mentioned copy&paste mistake in the reset branch of the avawr process.

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From early time of cmos I remember this: everything is clocked and is a cmos device has near zero power draw when f=0 but power raise with square of frequency, this at time of TTL and STTL, HC HCT crossed the power of old standard just near 1MHz, at that time FPLA PAL PLD CPLD where power hungry and leaving something active was driving die very hot. Maybe nowadays tools move process on register change and/or provide clock enable or simple feedback logic, so old school was to optimize for power too, I just do some check to see power planner. I am now using operator than old logic equation to generate logic so TOOLS are more smarter and last 15/20 year of development changed mode of thinking too and last but not least languages.

This time I am quite busy, I try see some different approach with large registers and check power draw.

regards

Roberto

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Power consumption in a CMOS circuit rises proportional to the frequency, not to its square. The square is in the voltage-dependent factor. See e.g. here (just a random hit): https://www.ece.cmu.edu/~ece322/lectures/lecture13/lecture13.03.pdf (slide 7). To really save power, you would need to completely cut the clock signal from parts of the design. Doing this for large things like a processor core or an audio/video decoder may be reasonable, but definitely not for a single adder. Inserting clock switches may cause quite some synchronization problems due to the added clock skew.

I would be happy to see your improvements to the posted code, though.

Regards,

Philipp