interface a module with avalon bus

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This is left as an exercise for the reader ;) In fact, this component does not serve any real purpose anyways, so I've just omitted additional features. Byte addressing would need additional consideration anyways, as this would basically lead to kind of vector processing by packing four independent additions into one word or something similar.

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Hi Philipp, sorry for but I disagree that, our poster is just a beginner and wrong coding can confuse a lot, yes your code has type conversion and can work, I seen no declaration just during check for operand type, addition on code from poster cannot be done using std_logic_vector.

VHDL is strong typed and far from be a simple language we are using here the HDL part so during learning need have hint and example to grasp how to implement right way without inferencing latch and or other trap of.

Also programming and simulation part are far from other languages I feel few people can know in its entirety.

So guide and hint to help get right direction on huge amount of user manual and handbook.

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This is an FPGA, not a microcontroller where you can just "skip" an operation when it's not used. The adder is needed anyways, so it will always draw static power. As long as the input data doesn't change, there is no additional dynamic power. The only thing which is always clocked is the result register, but adding additional logic to enable it only when something changed will most likely increase consumption. I doubt that any of these would actually be measurable, though.

Bye,

Philipp

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From early time of cmos I remember this: everything is clocked and is a cmos device has near zero power draw when f=0 but power raise with square of frequency, this at time of TTL and STTL, HC HCT crossed the power of old standard just near 1MHz, at that time FPLA PAL PLD CPLD where power hungry and leaving something active was driving die very hot. Maybe nowadays tools move process on register change and/or provide clock enable or simple feedback logic, so old school was to optimize for power too, I just do some check to see power planner. I am now using operator than old logic equation to generate logic so TOOLS are more smarter and last 15/20 year of development changed mode of thinking too and last but not least languages.

This time I am quite busy, I try see some different approach with large registers and check power draw.

regards

Roberto