interface a module with avalon bus

Hi Phlibi, I read over your code, it can help understand how to interface avalon Bus but at first glance it has some flaws:

Registers are 32 bit wide-

No byte addressing is provided on

No status register is provided to check for overflow

On avalon write part:

if reset = '1' then

dac_value <= (others => (others => '0'));

elsif rising_edge(clk) then

this code reset an undeclared dac_value, I don't see declared on your code post, others is used two times as if op_a was an aggregate so I think about syntax error, IMHO it has to reset op_a and op _b so must look as it follow --- :

this version generate an asyncronous reset and probably a latch.

if rising_edge(clk) then

if reset = '1' then

op_a <= (others => '0');

op_b <= (others => '0');

else

Process calc is active forever, it is required just when you write one of operand, this save a lot of power.

Regards