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Altera_Forum's avatar
Altera_Forum
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10 years ago

interface a module with avalon bus

Good evening; i want to know how to interface a module HDL with the avalon bus if any one can answer me Thank you
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

--- Quote Start ---

this is the code iam trying to use

BEGIN

to_adder <= writedata;

--WITH (chipselect AND write) SELECT

adder_instance: adder PORT MAP (clock, resetn, to_adder, from_adder);

readdata <= from_adder;

--- Quote End ---

Any progress on this part?

Avalon read write data on rising edge of clock, also reset_n is better if implemented on, other signals: readdata, writedata tell logic about data direction, cs tell your module it is selected and address in yor case select one of four register. You need also test byteselect vector too.

Did you learnt something from 32 bit register example?

Regards