Interconnect issue

I presume you are using Qsys and these are two custom components. Is that correct? The Avalon spec doesn't have a "read request" signal, so in the Qsys component editor, what signal role have you given this signal? Do you mean that it's a "read" (i.e. read enable) signal? Check the Avalon spec here: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf