Hi Benedict
This is Majid Safavi, I am the Thermal design FAE for Intel FPGA products. Below are my answers to your questions in order.
- There should not be gap, there may have been some issues with the import, However it should not impact the results since there is almost no heat transferred from the bottom
- Yes , add the thermal properties to all different materials in the model and add the power of each die from the EPE or PTC calculator. A file with all the thermal properties should have been sent to you.
- That is correct.
- That is correct and the numbers only apply to the design in hand, any changes in design can cause the TTDP or ψJC values to. So each design has its own unique values
- just apply the power calculated for a given die to that die evenly. It looks like your device has 5 dies, Core fabric and and 4 transceivers, each gets its own power
- That indicates that heat from the other dies are flowing into that die, it is perfectly normal to see that.
- What is the part number and can you also email me the CTM and the material property sheet that you have, My email address is majid.safavi@intel,com
Please also send me the part number that you are using.
BR,
Majid Safavi
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