Forum Discussion

AK-1's avatar
AK-1
Icon for New Contributor rankNew Contributor
4 years ago
Solved

Intel Stratix 10 GX Ethernet Hard IP

Hi, I'm planning to use Intel Stratix 10 GXs inbuilt 10G ethernet HARD IP Phy and interface it to an optical transceiver. Based on Intel Stratix FPGA document, we can configure single channel of...
  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
    4 years ago

    Hi Aravind,


    Apologize but I couldn't give a confirmed answer on your query as its out of my expertise. But I would suggest that it will better to re-evaluate the board design again. I guess even though its 0.09V voltage change, it might have some impact.

    You may need to discuss with your board designer to determine if it still meet the spec since the datarate also become faster.


    Regards,

    Pavee


paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

Hi Aravind,


Apologize but I couldn't give a confirmed answer on your query as its out of my expertise. But I would suggest that it will better to re-evaluate the board design again. I guess even though its 0.09V voltage change, it might have some impact.

You may need to discuss with your board designer to determine if it still meet the spec since the datarate also become faster.


Regards,

Pavee


AK-1's avatar
AK-1
Icon for New Contributor rankNew Contributor
4 years ago

Hi Pavee,

Thank you for your answers, it helped me a lot!

We are planning to use E-tile itself

Thanks & regards,

Aravind D

  • AK-1's avatar
    AK-1
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi Pavee,

    Hope I can get your support once again!

    How many I2C and SPI we can use in Intel stratix 10 FPGA, is there any limitation?

    If we use one spi(MISO,MOSI,CLK) with 6 chip select pins it will act as single SPI only rite?

    Thanks & regards,

    Aravind D