Forum Discussion
New ContributorIntel Stratix 10 GX Ethernet Hard IP
Hi Aravind,
Apologize but I couldn't give a confirmed answer on your query as its out of my expertise. But I would suggest that it will better to re-evaluate the board design again. I guess even though its 0.09V voltage change, it might have some impact.
You may need to discuss with your board designer to determine if it still meet the spec since the datarate also become faster.
Regards,
Pavee
Frequent ContributorHi Aravind,
Thanks for the clarification. If you want to use specifically H-Tile Ethernet Hard IP, then you can't be able to use for your requirement which is 10G as H-tile Ethernet Hard IP only supports 50G and 100G.
Link below explains on Tile and IP core support. Kindly refer to Table 1 - Device and IP Core Support.
Regards,
Pavee
New ContributorHi Pavee,
Thanks for the confirmation!
We planned to use 100G (as it will give room for future improvisation also) along with an optical transceiver which supports 100G.
Please refer below table 10 from Intel stratix 10 device datasheet.
In this they have mentioned for speed range 1 to 28.3 Gbps (GXT) typical voltage level for transceiver bank is 1.12V.
Currently we have designed for 1.03V, if i change from 1.03V to 1.12V (roughly 0.09V)
Do we need to do the PDN analysis and re design the FPGA decap section or we can maintain the same, as it is a minor voltage change!
Kindly provide your suggestion!
Regards,
Aravind
