Forum Discussion
New ContributorIntel Stratix 10 GX Ethernet Hard IP
Hi Aravind,
Apologize but I couldn't give a confirmed answer on your query as its out of my expertise. But I would suggest that it will better to re-evaluate the board design again. I guess even though its 0.09V voltage change, it might have some impact.
You may need to discuss with your board designer to determine if it still meet the spec since the datarate also become faster.
Regards,
Pavee
Frequent ContributorHi Aravind,
Apologize for not be able to see the picture attached in previous reply. I have attached the link below. Kindly refer to page 12 for the Single 10G/25G Channel block diagram.
For reference clock, I would suggest you to use 156MHz or 332.5Mhz. Its depend on your design. Kindly refer to 2.11.17. Clocks page 159-161. It explains more on usage of clocks based on configuration.
Kindly do let me know if it helps.
Regards,
Pavee
AK-1Hi Pavee,
Thanks a lot for your effort!
Actually we are planning to use Intel Stratix 10 FPGA with H-tile(as it supports Ethernet Hard IP) transceiver speed grade -3.
In H-tile Hard IP user guide, in that FPGA with speed grade -1 or -2 only supports 100G or 50G Ethernet(it is obvious than only at least with GX we can get 10Gbps per channel)
My question is as we require only 10G speed, can we go with H-tile with speed grade -3(it can give 17.4 Gbps in Enhanced PCS mode in GX, since speed grade -3 doesn't support GXT).
Kindly confirm whether my understanding is correct & your suggestion.
Regards,
Aravind
