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AK-1's avatar
AK-1
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4 years ago
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Intel Stratix 10 GX Ethernet Hard IP

Hi, I'm planning to use Intel Stratix 10 GXs inbuilt 10G ethernet HARD IP Phy and interface it to an optical transceiver. Based on Intel Stratix FPGA document, we can configure single channel of...
  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
    4 years ago

    Hi Aravind,


    Apologize but I couldn't give a confirmed answer on your query as its out of my expertise. But I would suggest that it will better to re-evaluate the board design again. I guess even though its 0.09V voltage change, it might have some impact.

    You may need to discuss with your board designer to determine if it still meet the spec since the datarate also become faster.


    Regards,

    Pavee


paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

Hi Aravind,

Based on your description, your understanding is correct on single channel 10G Ethernet.

Below I have attached the single 10G/25G channel blockdiagram for your reference.


Kindly do let me know if it helps.


Regards,

Pavee




  • AK-1's avatar
    AK-1
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi Pavee,

    Thank you for your response!

    The block diagram is not visible for me, if you share me link for the blk diagram i will look in to it.

    One more question regarding - Provide locally generated 332.5 MHz ref clock for the respective transceiver bank in which Ethernet

    signals are connected.

    whether 332.5Mhz is okay or we need to use 156MHZ or 644.5Mhz!

    can you also help me to understand how this frequency value for Ethernet signals are determined or fixed?

    Regards,

    Aravind