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jasmel's avatar
jasmel
Icon for New Contributor rankNew Contributor
3 years ago

Intel MAX 10 FPGA doesn't support LVTTL at 3.3V with a VOL (max)= 0.40V??

Hello We would like to use the Intel MAX 10 FPGA to drive a 3.3V LVTTL as a JESD8-B. But the datasheet doesn't show that compatibility: VOL(max) = 0.45V, which do NOT follow the JESD8-B requirement...
_AK6DN_'s avatar
_AK6DN_
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

I think you will find that the Altera standard spec on all their datasheets for 3.3V LVTTL is 0.45V max at 4ma.

For 3.3V LVCMOS is is 0.2V at 2ma.

Same spec for CycloneIV, CycloneV, MAX10.

If I look at some Xilinx datasheets, they tend to spec their 3.3V LVTTL as 0.40V max at maximum drive level.

So my guess is JESDB spec writers were a bunch of Xilinx users and just took their spec sheet numbers.

If you can't accept the extra 50mV on the worst case then add an external high current driver.

You will find the typical Vol is normally much less than 0.45V for 3.3V LVTTL at the spec'ed load of 4ma anyway.