New ContributorHi,
It looks like the TDI and TMS are internally pulled up to VCCIO (3.3V), but when we want to flash the FPGA through intel download cable, the voltage levels are all at 2.5V. This will cause a conflict in voltage levels? Is there a way to disable the internal pull ups on these 2 lines?
Thanks,
Priya
Regular ContributorHello,
Please refer to this : https://www.intel.com/content/www/us/en/docs/programmable/683546/current/pull-up-and-pull-down-of-jtag-pins-during.html
You can't disable the internal weak pullup. You can change the VCCIO of the IO bank or change VCC of the JTAG signal.
Side notes: There will be no contention between 3.3V and 2.5V as the Vih/Vil is the same.
regards,
Farabi
Regular ContributorHello,
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
regards,
Farabi
