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ats52's avatar
ats52
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3 months ago

Intel Arria10 GX Development Kit - DDR3 example design - traffic_gen_fail

Hello. I'd like to ask a question about DDR3 example design for Intel Arria 10 GX Development Kit (DK-DEV-10AX115S-A). I'm facing at the traffic generator test failure (traffic_gen_fail = 1) after ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 months ago

Hi ats52,


"If I suppose you have an Arria 10 GX Development Kit board, the project I attached works fine on your board?"

  • Currently we have some hardware limitation to test the design. Thus, I cannot test the design you provided.


"As far as I've looked into the installer package of arria10GX_10ax115sf45_fpga_v22.4.0_v1.1.zip, it looks only SOF files are included for BTS items, the project designs are not. Is it possible to get the project design for BTS of DDR3? Since BTS and the example design test for DDR3 make difference, I hope I will be able to find some clues if the project is available"

  • You can use the design from "arria10GX_10ax115sf45_fpga_v22.4.0_v1.1.zip\arria10GX_10ax115sf45_fpga_v22.4.0_v1.1\examples\memory\PRD\qts_ddr3_x72_1066MHz" to run the test.
  • I think it's similar to BTS design.


Regards,

Adzim


  • ats52's avatar
    ats52
    Icon for New Contributor rankNew Contributor
    3 months ago

    Hi AdzimZM

    Thanks for the information about the BTS design. Indeed it is there in the archive.

    I have compared the EMIF IP configuration between the generated example design and the DUT in BTS.
    There are not that many parameters different from each other, however they does make difference.

    I have applied to the following configuration parameters of BTS to the EMIF DDR3 IP in the example design, in addition to the design itself differences (address width, ECC enable/disable) etc.

    Tabsub categoryparameter nameemif_0 (example design)ed_synth_dut_0 (board support test)
    Mem I/OMemory I/O SettingsODT Rtt nominal valueODT DisabledRZQ/2
    　-　-Dynamic ODT (Rtt_WR) valueRZQ/4Dynamic ODT off
    FPGA I/OAddress/CommandOutput mode12 mA8 mA
    - -　Slew rateunsetFast
    -Memory ClockOutput mode12 mA8 mA
    -　-Slew rateunsetFast
    Mem TimingParameters dependent on Speed Bin, Operating Frequency, and Page SizetRRD67
    　-　-tFAW25.035.0
    　-Parameters dependent on Density and TemperaturetRFC160.0260.0

    Now I got the successful result with both local_cal_success and traffic_gen_pass.

    Thank you for your support.

    Best regards,