Integrate the Opencores's I2C ip into SOPC

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originally posted by tom@mrg@May 15 2006, 03:16 AM

hi, if you get the document on the i2c core at opencores, it says you can just export the reset pin and tie it low.

with the two chipselects, just ignore the error - sopc just connects both to chipselect anyway (you can see this in the ptf)

But[/b], you will find it will not compile in quartus Because of the &#39;generic&#39; problem covered above. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

If you repeat the process using the &#39;oc_i2c_master_top&#39; provided by FMousset above, you not only get a core that is easier to attach to the NIOS but it compiles and there is no need to mess about with the tristate buffers etc.

So the way I made it work is as follows:

1) I downloaded " i2c_master_bit_ctrl.vhd, i2c_master_byte_ctrl.vhd and i2c_master_top.vhd" from open cores

2) I pasted FMoussets code into notepad and called it oc_i2c_master_top.vhd (NO CAPITAL LETTERS) Thanks to FMousset for the code!

3) In SOPC builder I created a new component using the oc_i2c_master_top as the VHDL source file. No other changes are required, as all the signals are already set up http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

4) Put the newly created &#39;oc_i2c_master&#39; into your sopc and generate.

5) Attach two bidir pins to the scl and sda outputs from the sopc and you are done!

We are running it in a 2C35 with no problems (so far!) http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

Hope this helps

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[/b]

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http://via.fps-tech.org/svn/fpga/cores/i2c_master/trunk/ (http://via.fps-tech.org/svn/fpga/cores/i2c_master/trunk/)

A ready made avalon component - no need to do all of this.