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Altera_Forum
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15 years ago

Integer to Bit Vector VHDL code error

I'm new to VHDL and I am trying to convert an integer to a 14 bit vector. Here is the protion of my code. gear_calc <= to_integer(unsigned(to_stdlogicvector(Input_2))); synchro_g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

yes, you can use integer for entity input and outputs (but not at the top level). And yes, giving it a range of 0 to 2**14-1 will limit it to 14 bits. If you dont put a range, it will use 32 bits, but if the top bits are never connected to anything, they should be snipped during synthesis. But putting a range is normally the safer option.