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Altera_Forum's avatar
Altera_Forum
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14 years ago

Integer to Bit Vector VHDL code error

I'm new to VHDL and I am trying to convert an integer to a 14 bit vector. Here is the protion of my code. gear_calc <= to_integer(unsigned(to_stdlogicvector(Input_2))); synchro_g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

why are you using bit_vectors anyway?

Second question, why are you doing such massive conversions? why not just stick with integers or unsigned?

This amount of type conversion can get very frustrating when you have to do it all the time. Its alot easier just to stay with the type, and keep associated signals in simular types.