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Altera_Forum
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15 years ago

Integer to Bit Vector VHDL code error

I'm new to VHDL and I am trying to convert an integer to a 14 bit vector. Here is the protion of my code. gear_calc <= to_integer(unsigned(to_stdlogicvector(Input_2))); synchro_g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

to_unsigned() takes a bit length as second parameter, it must be 14 in this case. A to_stdlogicvector() or to_bitvector() conversion has to be applied on the unsigned then.