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Altera_Forum's avatar
Altera_Forum
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14 years ago

Integer to Bit Vector VHDL code error

I'm new to VHDL and I am trying to convert an integer to a 14 bit vector. Here is the protion of my code. gear_calc <= to_integer(unsigned(to_stdlogicvector(Input_2))); synchro_g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

--- Quote Start ---

FOR i IN 0 to 16383 LOOP

synchro_gear_vect(13 DOWNTO 0) <= bit_vector(to_unsigned(synchro_gear,i));

END LOOP;

END IF;

--- Quote End ---

above loop will be unrolled by compiler to last case of i = 16383. All other cases will be overwritten.

regarding bit_vector, change them to std_logic and you are avoiding the old type