Instruct Quartus to put specific circuits together and minimize delays

1. What should I write to instruct fitter/assembler to lay cascaded embedded multiplier and accumulator out to be ready with math within, let's say, 3 cycles for further latching?

You may use the multy cycle in the SDC, I suppose you cannot add pipeline register?

Multi Cycle is not hard to understand, If you find difficulty to understand this, we can setup a call for you.

2. Is there any way to force Quartus to re-fit, or give hard error, if it can not lay out the circuit the way to satisfy the multicycle timing requirement?

Unfortunately, nope. But you can analyze the Timing analyzer waveforms. Once you had set the multicycle, the result will be reflected in timing analyzer

3. If I have tons of warnings in the TimeQuest analysis, how do I find the ones I really care about? (^F does not work in the "Compilation report" window).

You can suppress the warning message, https://www.youtube.com/watch?v=NHsprt0UKEw