Thank you. Not sure I can write anything useful into SDC file immediately using these guides, however the matters are more or less clear. The TimeQuest analyzes the already fitted and assembled design for timing violations. I ask to instruct fitter upfront to place stuff the way they it does not violate the timing.
My case is super simple. Let;s imagine I have the following circuit:
multiplier multiplier (
.dataa(r_input_a[31:0]),
.datab(r_input_b[31:0]),
.result(w_output_result[63:0])
);
and then, in always construct, driven with the same clock for launch and latch:
wire w_accumulator[70:0] = w_accumulator[70:0] + { {6{1'b0}}, w_output_result[63:0]}};
r_input_a and r_input_b are latched on the clock edge, and accumulator is latched into another register several cycles later - using the same clock. All signals are internal, no pins are involved.
1. What should I write to instruct fitter/assembler to lay cascaded embedded multiplier and accumulator out to be ready with math within, let's say, 3 cycles for further latching?
2. Is there any way to force Quartus to re-fit, or give hard error, if it can not lay out the circuit the way to satisfy the multicycle timing requirement?
3. If I have tons of warnings in the TimeQuest analysis, how do I find the ones I really care about? (^F does not work in the "Compilation report" window).
Update: I have learned from your reply about multicycle constraints, thank you for this. Found
this document, but it is beyond my understanding, and I will not be able to properly design the statements using it. In the past I was trying to constraint clocks in SDC file, and whatever I was putting into there was causing an error, thus I gave up and decided that I would better make circuits free of timing problems by design rather than learn how to
properly instruct software to fix the timing in design.
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