input to IIR filter in Verilog

Thanks Kaz!

module test_filter(clk,filter_in,filter_out);
                
parameter W=7;    // bit width - 1
parameter signed a=10'b0100000000;
input   clk; 
input   signed  filter_in; 
output  signed  filter_out;
reg signed  x,y;
initial
begin
    x=0;
    y=0;
end
    
always@(posedge clk)
    begin
    x <= filter_in;
    y <= ({x,10'b0000000000}) - (a*x) + (a*y);    // y=(1-a)*x+(a*y)
    end
        
assign filter_out=y;
endmodule  // test_filter