input to IIR filter in Verilog

Thanks for both of your replies! Cleared a few things up! :)

I really should explain what I'm trying to do:

All I want to do is implement a simple low-pass filter to attenuate all harmonics (except the 1st - the fundamental) from an guitar audio signal when a string is plucked - i.e. I'm making a digital guitar tuner.

I've designed all the other components of the circuit and am now just trying to get the filter working.

A low order IIR low-pass should be fine and shouldn't be too hard to implement...

I'm just trying to figure out what to do with the fractions!

For example:

module test_filter(clk,filter_in,filter_out);
                
parameter W=7;    // bit width - 1
parameter signed a=0.7;
input   clk; 
input   signed  filter_in; 
output  signed  filter_out;
reg signed  x,y;
initial
begin
    x=0;
    y=0;
end
    
always@(posedge clk)
    begin
    x <= filter_in;
    y <= (1-a)*x + a*y;
    end
        
assign filter_out=y;
endmodule  // test_filter

This is just a test IIR filter I wrote - my question is:

How would Verilog treat the 0.7 in the above code?

Would the value of y be rounded?

Do I need to add extra code if I want to multiply by fractions?

(Also, my output from the ADC is now 8-bits (two's complement)! ;))

Cheers,

Nick