input to IIR filter in Verilog

Hi,

The above replies may sound confusing to beginners. Let me add this. My reply seems to be the hardware perspective while FvM reply seems to be the DSP(software perspective).

The dsp perspective sees the values as 1 and its fractions e.g. a gain of 1 applies to an input that swings between(1, -1 across all fractions).

I find it much more practical to follow the notion of hardware values directly.

I mean: an input of 16 bits will swing between +32767 and -32767 across all integers(no meaning for fractions). the coeffs will similarly swing across their resolution of say 32767/-32767.

multiplication with full room for bit growth means upscaling to +32767^2,

additions add further bits, 1 bit per stage assuming room for full bit growth. The final output is then truncated back n bits(divided by 2^n) into 16 bits with optional rounding.

The above computations does not mention filter gain. this can be tackled at coeffs scaling which need not be represented to the roof if you want unitary gain...

It then remains up to you or other's tools to define the terminlogy.

Remember Matlab tool is designed by software engineers with the mindset of +1 and I don't see why they should not try to see the hardware perspective when it comes to hardware deisgn.