input to IIR filter in Verilog

Hi,

Firstly, your input of 24 bits looks too much to me unless you have some other reasons for this extra high and expensive resolution.

I am not familiar with using the terms of word length and fraction length but I feel sure it means:

word length = your signal resolution (at input/final output).

fraction length = the extra bits you want internally for computation before final output is truncated back. You may choose to cover results fully at each stage of computations e.g. 16 bits * 16 bits needs 31 bits(or 32 if you wish),

31 + 31 + 31... needs 33 bits, this can be termed a fractional width of [33 - 16 = 17], anything more is void.

You can do things manually and this gives you better understanding which is the vital thing taken away from you by tools terminology.

get your coeffs in floating format(fractions of 1), upscale it to your resolution with rounding. make your internal output width wide enough then truncate back to your signal width (with rounding).

In any case if your computation result is > available width you must clip(not recommended).