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BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5

Hi, I am trying to interface the FTDI601 USB Bridge (https://ftdichip.com/products/ft601q-b/) to the Stratix 10 1SG10MHN3F74C2LG_U1/U2 FPGA on our design board. The reference clock for the interface...
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Generic Io
BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi Aqid,

Thanks for you help. I did not get any concrete solution from FTDI too. I think its the delay of the board. With OE taking its time to travel and data taking its time to travel back so that makes RXF_N to apper valid for a cycle longer. Anyways. you can close this request.

Thanks

Bharat