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Altera_Forum
Honored Contributor
16 years agoInput pin not found using get_ports command
Hello All, Here is my problem. I am trying to constrain one of my input clock ports (pll_1705_mclk) for timing analysis using Timequest but when i use the "get_ports" command i get this error ...
Altera_Forum
Honored Contributor
16 years agoSynthesis always tries to optimize logic. The most common examples are when your logic doesn't drive an output, then all the upstream logic gets synthesized away. Another example is if you forget to hook up an input(on designs with hierarchy, where you instantiate something but don't drive all the inputs), then the downstream logic can get synthesized away. It can be a lot more complicated than that. A large case statement might have conditions that will never evaluate to true, though you think they will, and hence that state and anything based on it gets removed. Start going through the messages and synthesis reports.