Input Clock Rate Selection

If your PLL fails due to bad layout with 64 MHz, I won't give a damn for better behavior with 8 or 16 MHz clock. That's because it's mostly the clock edge quality which causes the problems as long as the clock level is halfway correct. Anyway I would suggest a low clock frequency like 8 or 16 MHz, crystal oscillator power consumption and EMI are sufficient reasons. Don't forget an impedance matching series resistor at the oscillator to avoid overshoot and double edges.

The clock frequency range doesn't affect PLL resolution and jitter with recent FPGA families, because the input frequency can be divided before the phase detector. PLL jitter is mainly caused by the VCO and several orders of magnitude larger than of a good crystal oscillator.