Inout questions in testbench

ok I have another question on this issue.

now it works, but if I write:

tdata_dsp <= (others => 'Z');

modelsim thinks that it's like I force tdata_dsp to Z. So, when I enable the writing on the bus it writes, but when I remove the enable, tdat_dsp returns Z...

so it's like tdata_dsp is always a input, except when I enable the write...

I would like that when I enable the write, tdata_dsp changes its status to an output, until it will return an input (if this happens).

Anyway, my doubt is: is this a problem of the testbench, or I will see a similar behaviour even in real?