Inferred RAM Coding

How can we infer the following memory module as RAM instead of register array ?

https://github.com/promach/internal_logic_analyzer/blob/master/rtl/memory_block.v

I have tried to modify, but some inevitable warnings are shown. http://quartushelp.altera.com/14.1/mergedprojects/msgs/msgs/wtdb_analyze_comb_latches.htm

(http://quartushelp.altera.com/14.1/mergedprojects/msgs/msgs/wtdb_analyze_comb_latches.htm)

`include "define.v"   
module memory_block (clk, write_enable, waddr, raddr, data_write, data_read);   
input clk, write_enable; 
input  waddr; 
input  raddr; 
input  data_write;  // data to be written into memory 
output reg  data_read;  // data read out from memory   
reg  memory ;   
always @(*) begin     
    if (write_enable)            
        memory = data_write; 
end   
always @(*) begin     
    if (!write_enable)           
        data_read = memory; 
end   
endmodule

https://alteraforum.com/forum/attachment.php?attachmentid=14134&stc=1