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AlteraUsr
New Contributor
New ContributorIndependent clock mode True Dual port RAM in Agilex
I need to use a true dual port RAM with separate clock for each port. This used to be possible in Arria 10 (where M20K was used), but in Agilex, I see that apart from required number of M20Ks, a whol...
Nurina
Regular Contributor
Regular ContributorHi,
I'm not sure why this RAM takes up a lot of ALMs after migration. Try changing some of the parameters (RAM block type, maximum block depth) and re-generate the RAM IP. Make sure your parameters are correctly set, please refer to Table 24 in this documentation for suggested parameter settings: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/agilex/ug-ag-memory.pdf#page=44
Regards,
Nurina
