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Altera_Forum
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13 years ago

Indefinite states of State Machine - VHDL

Hi Guys, I would like to ask for your help... I wrote a simple code that is identifying the rising edge of incoming signal. There are two states - every time that rising edge existing, the st...
Altera_Forum's avatar
Altera_Forum
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13 years ago

I suppose your incoming signal is asynchronous to your processing clock. As such it will have a different propagation delay to each register in the state machine and in the end each of the state-machine registers may see a different level, and possibly clock in an invalid transition ending up in an undefined state.

So you have to synchronise this external input with a two-stage register chain to avoid this (and metastability) issue.