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Altera_Forum's avatar
Altera_Forum
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15 years ago

Incrementing loop index in vhdl generate statement

Hi,

I am working on an HDL for an Altera design. I came a situation where i want to increment vhdl generate loop index by 2.

An example is show below,

LABEL: for i in 1 to CNTR_WIDTH -1 generate

REG1(i) <= ORG_REG(i)(1 downto 0);

REG1(i+1) <= ORG_REG(i)(3 downto 2);

end generate;

I want the generate loop i variable index proceeds like 0,2,4,6 upto the defined range.

Please help me how to do this in vhdl?

Regards,

Jaseel

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    just multiply i by 2

    REG1(i*2) <= ORG_REG(i*2)(1 downto 0);

    REG1(i*2 +1) <= ORG_REG(i*2)(3 downto 2);
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Jaseel

    I'd have suggested the same as Tricky... but he was faster in replying.

    If you don't like the i*2 solution you can use a while loop instead of for, so you can increment what you want.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Hi Jaseel

    I'd have suggested the same as Tricky... but he was faster in replying.

    If you don't like the i*2 solution you can use a while loop instead of for, so you can increment what you want.

    --- Quote End ---

    you cant use while loops for a generate statement