Importance of Impedance Matching

Generally, you can expect that FPGA family output drivers (including MAX II) are fast enough to cause overshoot even on rather short, e.g. 2" or 50 mm traces. Adjusting the drive strength and - sometimes necessary - addig external series resistors can manage the issue.

Drive strength reduction can be seen as slowing down the edges in connection with the sum of load and pin capacitance or as adjusting a series source sided transmission line termination. For longer traces, the latter view gets physically evident to my opinion, although an additional capacitive load should be considered in an exact transmission line based analysis.

Beneath source sided termination, also load sided and any kind of hybrid termination is possible. A pure resistive load termination has the disadvantage of creatig high losses and is generally used only with high speed I/O standards. A RC load in contrast, causes some kind of complex mismatching, but can be adjusted for optimum pulse shape. Finally, if unmatched T connections respectively stubs are involved, smaller (a few 10 ohm) series resistors at the branch can at least reduce multiple reflections. They sometimes allow a fair signal quality with topologies, that should never exist following the transmission line theory.