Honored Contributor
Honored ContributorThank you all very much for your replies. This thread has set me off on the right research track to answer many of my questions. As is often the case however, more questions did arise out the process.
I now understand digital signal integrity to be a process involving the following issues: Impedance Matching Transmission line parameters Ringing Overshoot Crosstalk Skin Effect And I've now got a decent handle on how all of these work and are related, with exception of ringing, which there doesn't seem to be a lot of consistant information online about as it pertains to digital systems. Anyone want to chime in? Finally, many of the equations I've seen about signal integrity involves knowing the rise time of signals in order to determine their bandwidth, but the rise time of the MAX II and the oscillator I'm using (20 MHz) are not published. Altera stated the following in a white paper: The maximum rise and fall times for input signals are application dependent and vary based on the system and device noise and on the timing margins on the interface. Because of this dependency, Altera does not provide the maximum rise and fall time specifications for the following devices: ■ Stratix® II, Stratix, and Stratix GX devices ■ Cyclone® II and Cyclone devices ■ HardCopy® series devices ■ APEX™ II and APEX 20K devices ■ MAX® II devices Anyone have a rule of thumb that they use or any insight to shed on the subject? Thanks a million, Jon
