Implementing FFT with NIOS

Greetings,

I am implementing a design that requires a 16384-point FFT, with 16-bit precision. In an attempt to get this design working, I first started with a 1024 FFT, and got it working perfectly. However, when I scaled it up to 16384, I ran into some issues because the SGDMA interface is limited to 64-bits; but my FFT's output was 68-bits (34 for real, and 34 for imaginary). The following lists the design and components that I am using:

• FFT

• 16384 Point

• 16-bit precision/twiddle

• 34-bit real output

• 34-bit imaginary output

• Encapsulated inside of a wrapper the a has 4 interfaces

• 1 MM slave

• 1 Avalon streaming sink

• 2 Avalon streaming sources

• 1 for the real output

• 1 for the imaginary output

• NIOS II/f process

• 3 SGDMAs

• 1 to interface with processor for loading input data to the FFT

• 1 to interface with processor for reading real output data (34-bits)

• 1 to interface with processor for reading imaginary output data (34-bits)

• 1 Input RAM

• Loaded through software using SGDMA interface

• (C code -> SGDMA interface(MM to ST) -> RAM )

• 2 Output RAMs

• Loaded with the output from the FFT, via the SGDMA

• (FFT -> SGMA interface(ST to MM) -> RAM)

Is there any other clever way to get around this issue? I could use the 1024 point FFT implementation, but my signal requires a much larger FFT to obtain proper results.

Basically I need to tweak the SGDMA to handle > 64 bits of data. When I split the real and imaginary part up, the output SGDMA's never finish. Any help would be greatly appreciated.