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How many of the bits would be accessed at once in a single cycle? More generally, what is the access pattern? Can you reorganize the data in such a way that bits are grouped into tall "columns", and, in any clock cycle, there's at most 2 accesses (2 writes or 1 read and 1 write) to each column?
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Yes. The pattern is 2 writes in a single cycle to the same column in some particular pattern such that the column get filled, then moving-on to filling the next one.
After the table is full there is a read of a single bit from the last (1006th) column, then another single bit from the 1005th column (row is determined by the previous bit extracted), and so on.
So the read have to be 1-by-1, as the next "row address" to read from depends on the value from the previous read.
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On that part you have 105 M4K blocks, which can be configured in a 4096x1 access thru 128x32. Since you only need a depth of 64 vs the smallest native depth of 128 it means you will need to build a memory that is twice as big, like (128x32)x32 slices to give a 128x1024 array, assuming you want to access all 1006 bits in parallel.
With 105 M4K blocks on that EP2C35 device you have more than enough M4K resources (105 >> 32).
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So what you are saying basically is to use multiple M4Ks and use muxes and other selection blocks to write\read to\from the appropriate block.
A follow-up question to you:
If I use HDL to decribe such a 64 X 1024 array of bits, will the synthesizer "know" to build the selection circuitry needed?
Or is the right way of doing it is specifying exactly the use of 32 M4Ks and the proper selection circuitry by myself?
Thanks a lot to both of you!
Honored Contributor
