Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Implementing a Large RAM on Cyclone II - is it possible?

Hi, this is my first time implementing something on FPGA. My instructor is currently very busy and I can't find an answer to my problem, hoped I would find here someone nice enough to help. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

On that part you have 105 M4K blocks, which can be configured in a 4096x1 access thru 128x32. Since you only need a depth of 64 vs the smallest native depth of 128 it means you will need to build a memory that is twice as big, like (128x32)x32 slices to give a 128x1024 array, assuming you want to access all 1006 bits in parallel.

With 105 M4K blocks on that EP2C35 device you have more than enough M4K resources (105 >> 32).