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Altera_Forum
Honored Contributor
Honored ContributorImplementing 18-bit lvds serializer in CPLD
Hello,
Maybe this is a beginners question. I do not yet have a lot of experience using CPLDs. They are a bit more limited than FPGAs. I was wondering if it is feasible to implement an 18-bit LVDS deserializer on a low cost FLASH CPLD. For a projet I need the deserializer and some simple glue logic. It would be perfect if this could be implemented in an all-in-one chip like one out of the MAX family. However, I am not sure about the clock recovery part. This probably needs a PLL of some sort. Can this be done in a MAX? Thanks in advance for any help. Ronald12 Replies
Altera_ForumQuite a pity. It would have been a beautiful solution. So what about the low cost FPGAs? Is it possible there? The solution would have a higher component count, but it might still be interesting.
Or does Altera already have FLASH FPGAs? How complicated is it to implement such a deserializer for 25Mhz parallel out? Do they have affordable IP for this?- Altera_Forum
Altera has announced a MAX V DPLL feature about two years ago, but there's apparently no software support until now.
http://www.alteraforum.com/forum/showthread.php?t=27399 So I won't rely on it for the time being. At lower data rates, oversampling may be able to recover the clock.
