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Altera_Forum
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13 years ago

Implementing 18-bit lvds serializer in CPLD

Hello, Maybe this is a beginners question. I do not yet have a lot of experience using CPLDs. They are a bit more limited than FPGAs. I was wondering if it is feasible to implement an 18-...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Altera has announced a MAX V DPLL feature about two years ago, but there's apparently no software support until now.

http://www.alteraforum.com/forum/showthread.php?t=27399

So I won't rely on it for the time being. At lower data rates, oversampling may be able to recover the clock.